1. Field of the Invention
The present invention relates to an information processor and a data communication control method, and more particularly to an information processor and a data communication control method capable of preventing problems in data communication resulting from breakdowns.
2. Description of the Related Art
Information processing systems are known in the prior art that include a control device that is connected to a peripheral device. In the information processing systems, when the control device suffers a breakdown, the control device is cut off from the peripheral device and the peripheral device then connected to another control device.
For example, information processing systems are described in Japanese Patent Laid-open Publication No. 211228/83 and Japanese Patent Laid-open Publication No. 243552/86 that include a switch unit that allows switching of the connections between a plurality of control devices and a plurality of peripheral devices. The information processing systems switch the connections between the control devices and peripheral devices by using the switch unit.
However, when the control device includes an arithmetic processor and an input/output processor for performing data communication with a peripheral device, the information processing systems suffer from the problems described below.
When a break-down occurs in the input/output processor while the arithmetic processor is operating normally, the normal arithmetic processor is cut off from the information processing system, resulting in the problem that a normal arithmetic processor cannot be effectively used.
An information processor that can provide a solution to this problem is currently known.
FIG. 1 is a block diagram showing an example of this type of information processor.
In FIG. 1, information processor 1 includes: diagnostic processor 2, a plurality of logic cards 3 (logic card 3a and 3b); and a plurality of channel devices 4 (channel devices 4a and 4b).
Logic card 3a includes: a plurality of arithmetic processors 3a1 (arithmetic processors 3a1a-3a1c), input/output processor 3a2, and memory 3a3. Logic card 3b further includes: a plurality of arithmetic processors 3b1 (arithmetic processors 3b1a-3b1c), input/output processor 3b2, and memory 3b3.
Diagnostic processor 2, logic cards 3a and 3b, and channel devices 4a and 4b are interconnected by bus 5. In addition, arithmetic processors 3a1a-3a1c, input/output processor 3a2, memory 3a3, arithmetic processors 3b1a-3b1c, input/output processor 3b2, and memory 3b3 are interconnected by bus 5.
Input/output processor 3a2 is placed in a fixed correspondence with channel device 4a. Input/output processor 3b2 is placed in a fixed correspondence with channel device 4b. Channel device 4a is connected to peripheral device 5a. Channel device 4b is connected to peripheral device 5a. 
Input/output processor 3a2 controls channel device 4a to perform data transfer with peripheral device 5a. Input/output processor 3b2 controls channel device 4b to perform data transfer with peripheral device 5a. 
As an example of the operation of information processor 1, when software, which operates on any arithmetic processor in logic card 3a, performs data transfer between peripheral device 5a and memory 3a3, the software provides data transfer instructions, which designate channel device 4a that corresponds to peripheral device 5a, to the arithmetic processor in which the software is operating. Upon receiving the data transfer instructions, the arithmetic processor provides data transfer instructions to input/output processor 3a2 that corresponds to channel device 4a. Upon receiving these data transfer instructions, input/output processor 3a2 performs data transfer with peripheral device 5a by way of channel device 4a. 
When input/output processor 3a2 suffers a breakdown, data transfer to peripheral device 5a that was using input/output processor 3a2 can no longer be executed.
However, information processor 1 operates as described below to continue data transfer with peripheral device 5a. 
Upon detecting the failure of input/output processor 3a2 that corresponds to channel device 4a, diagnostic processor 2 searches for another channel device (channel device 4b) that is connected to peripheral device 5a and then reports the search results to the arithmetic processor. The arithmetic processor reports these search results to the software.
When performing data transfer between peripheral device 5a and memory 3a3 after having received the search results, the software provides data transfer instructions that designate channel device 4b to the arithmetic processor. The arithmetic processor, in accordance with the data transfer instructions, provides the data transfer instructions to input/output processor 3b2 that corresponds to channel device 4b. 
As a result, the arithmetic processor uses input/output processor 3b2 to continue data transfer in spite of the failure of input/output processor 3a2.
In JP-A-H05-324950, a logic card is described that can store error information.
In information processor 1, input/output processors are placed in fixed correspondence with channel devices, and as a consequence, the following problems occur in information processor 1.
For example, in the event of a failure of input/output processor 3a2 that corresponds to channel device 4a when peripheral device 5a is connected to only channel device 4a, information processor 1 is unable to perform data transfer with peripheral device 5a. As a result, information processor 1 may become incapable of executing information processing.
In addition, in the event of a failure of input/output processor 3a2 when peripheral device 5a is connected to channel device 4a and channel device 4b, not only arithmetic processor 3b1 but also arithmetic processor 3a1 performs data transfer with peripheral device 5a by way of channel device 4b. As a result, the amount of data being transferred with peripheral device 5a by way of channel device 4b increases, leading to a potential drop in performance of information processor 1.
Information processor 1 plays an important role in the current IT community, and an operation halt or drop in the performance of an information processor can therefore have a serious impact on the entire community.